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Doctorate thesis defense of Souha SOUISSI

Doctorate thesis defense on July 13th 2016 at 09H00 AM ,in Amphi I, Sup’Com.

Entitled :Narrowband PLC channel characterization and modeling: Emulation platform design for Smart Grid applications

Presented by : Souha SOUISSI 




Professor, ENIT, Tunisia





Pr. Monia TURKI

Professor, ENIT, Tunisia


Pr. Dominique DALLET

Professor, IPB, France




Professor, SUP’COM, Tunisia


Thesis Director

Pr. Chiheb REBAI

Professor, SUP’COM, Tunisia




Industry Guest

Mrs. Wided MAALEL

Director of Control of Technology, STEG


The objective of this research work consists in proposing a flexible narrowband powerline communication (NB-PLC) channel emulator encompassing the channel bottlenecks which interfere during communication. The channel attenuation is deduced using bottom up approach and appropriate noise scenarios are defined to meet as much as possible realistic phenomena. The effect of zero crossing variation is also taken into account. The overall parameters are optimized to be embedded on a DSP platform.

Firstly, the bottom-up approach was investigated to provide a channel transfer function starting from the knowledge of physical parameter of a given powerline network. A Matlab based simulator was then developed. After that, the design of a coupling interface between the power line and the measurement instruments allowed us to build up an experimental set-up for measuring attenuation in some electrical network samples in the frequency band from 40 kHz to 500 kHz. Obtained measurements conducted us to verify the bottom-up approach adequacy for narrowband powerline channel. Secondly, the mains zero crossing (ZC) has been characterized using a dedicated measurement platform. Performed measurements over long periods in different environments allowed us to deduce an analytical model for mains ZC behavior using an autoregressive moving average (ARMA) model for each detected variation. The modeling was extended to three environment (rural, in-lab and in-home). Thirdly, an architecture of NB-PLC channel emulator was defined combining channel attenuation, mains ZC variation and noise. The used noise models were retrieved from literature. A cyclo-stationary model in combination with a damped sinusoid model was chosen to build a NB-PLC noise scenario. An implementation of the digital stage was then presented. An adaptation and tuning operations were applied for each block to fit the DSP based platform. An emulation setup was also defined based on proposed NB-PLC emulator.