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Doctorate thesis defense of Imèn DEBBABI

Doctorate thesis defense on May 2nd 2017 at 14H00 AM ,in Amphi, ISET'COM.

Entitled :LP decoding of LDPC codes: from algorithm to implementation

Presented by : Imèn DEBBABI 


Chairman of the Jury

Mohamed SIALA

Professor, SUP’COM, Tunisia






Professor, SUP’COM, Tunisia




Professor, FSM, Tunisia



Professor, INP-ENSEEIHT, France


Thesis Director


Associate Professor, SUP’COM, Tunisia



Christophe JEGO

Professor, IPB/ENSEIRB-MATMECA, France


Bertrand LE GAL

Associate Professor, IPB/ENSEIRB-MATMECA, France



Low-density parity-check (LDPC) codes have been the focus of much research over the past decade thanks to their near Shannon limit performance. As an alternative to message passing (MP) decoding, linear programming (LP) decoding is an approximation to maximum-likelihood decoding by relaxing the optimal decoding problem into a linear optimization problem. However, due to the inefficiency of general-purpose LP solvers, LP decoding is computationally more complex than MP decoding, especially for codes of large block sizes.

Recently, an efficient LP decoder has been proposed based on a popular distributed optimization method called alternating direction method of multipliers (ADMM). The ADMM approach exhibits much lower complexity than the previous LP techniques, has a message passing interpretation and has been demonstrated to have better error rate performance than both standard LP and BP algorithms. Hitherto, this innovative decoding technique has not been implemented on neither software nor hardware targets. Its complexity has not been estimated nor compared with traditional techniques.

The main objective of this thesis is to reduce the computational complexity of the ADMM l2 algorithm used in the decoding of LDPC codes. Then, to demonstrate the applicability of the LP approach by implementing the reduced complexity ADMM l2 algorithm on both software and hardware targets. The first step is to exploit the parallelism in the flooding scheduling to guarantee decoding rates that can meet the requirements of the WiMAX and WRAN standards. Then two layered schedulings are applied and optimized. We have proved that the horizontal layered scheduling helps the ADMM l2 algorithm to converge rapidly and to reduce its computational complexity without influencing its error correction performance. In addition, an implementation of the horizontal layered scheduling on a multi-core target enables the ADMM l2 decoder to achieve greater bit rates than 500Mbps, which proves the usefulness of the ADMM l2 algorithm for real-time applications. Finally, we implemented the ADMM l2 algorithm on a hardware target (FPGA) using an optimized fixed point representation of all the variables. The obtained architecture is compared (in terms of correction power, data rate and hardware cost) with those using sub-optimal algorithms. The on chip implementation results demonstrate the applicability of the ADMM l2 algorithm on hardware targets though the hardware cost is found to be higher than the BP based decoder. To sum up, the work done in this thesis demonstrates that ADMM l2 LDPC decoding can be a viable candidate for high correction performance in SDR systems.


LDPC, linear programming, alternate direction method of multipliers, iterative decoding, convergence, flooding scheduling, layered scheduling, software optimization, multicore, SIMD, SIMT, throughput, NISC, FPGA